`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
    
//detect 011100
localparam IDLE=8'b00000000;
localparam S1=8'b00000001;
localparam S2=8'b00000010;
localparam S3=8'b00000100;
localparam S4=8'b00001000;
localparam S5=8'b00010000;
localparam S6=8'b00100000;

localparam SF1=8'b10000001;
localparam SF2=8'b10000010;
localparam SF3=8'b10000100;
localparam SF4=8'b10001000;
localparam SF5=8'b10010000;
localparam SF6=8'b10100000;

reg [7:0]state;
reg [7:0]next_state;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		state<=IDLE;
	end
	else begin
		state<=next_state;
	end
end
always@(*)begin
	case(state)
		IDLE:begin
			//match=1'b0;
			next_state=(data==0)?S1:SF1;
		end
		S1:begin
			//match=1'b0;
			next_state=(data==1)?S2:SF2;
		end
		S2:begin
			//match=1'b0;
			next_state=(data==1)?S3:SF3;
		end
		S3:begin
			//match=1'b0;
			next_state=(data==1)?S4:SF4;
		end
		S4:begin
			//match=1'b0;
			next_state=(data==0)?S5:SF5;
		end
		S5:begin
			//match=1'b0;
			next_state=(data==0)?S6:SF6;
		end
		S6:begin
			//match=1'b0;
			next_state=(data==0)?S1:SF1;
		end
		SF1:begin
			//match=1'b0;
			next_state=SF2;
		end
		SF2:begin
			//match=1'b0;
			next_state=SF3;
		end
		SF3:begin
			//match=1'b0;
			next_state=SF4;
		end
		SF4:begin
			//match=1'b0;
			next_state=SF5;
		end
		SF5:begin
			//match=1'b0;
			next_state=SF6;
		end
		SF6:begin
			//match=1'b0;
			next_state=(data==0)?S1:SF1;
		end
		default:begin
			//match=1'b0;
			next_state=IDLE;
		end
	endcase
end
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        match<=1'b0;
		not_match<=1'b0;
    end
    else begin
        match<=state==S6;
		not_match<=state==SF6;
    end
end

endmodule